lowRISC / opentitan
OpenTitan: Open source silicon root of trust
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OpenTitan: Open source silicon root of trust
A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
Generic Register Interface (contains various adapters)
An energy-efficient RISC-V floating-point compute cluster.
Common SystemVerilog components
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
commit rtl and build cosim env
Test suite designed to check compliance with the SystemVerilog standard.
Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
A simple parametrizable doorbell based mailbox